Offset test pads for WLCSP final test
US10396001B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 15, 2016 |
| Grant date | Aug 27, 2019 |
| Priority date | — |
| Expiry date | Aug 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1443
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device configured for WLCSP, can include: a first pad; a test pad offset from the first pad; a first RDL path that connects the first pad to the test pad; and a second RDL path that connects the test pad to a solder ball. In another case, a device configured for WLCSP can include: a first pad; a test pad offset from the first pad; a first RDL path that connects the first pad to a solder ball; and a second RDL path that connects the test pad to the solder ball. A wafer having devices configured for WLCSP, can include: a first device having a first pad; a second device having a test pad; a first RDL path that connects the first pad to a solder ball; and a second RDL path that connects the test pad to the solder ball.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.