Layout pattern for SRAM and manufacturing methods thereof
US10396064B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2018 |
| Grant date | Aug 27, 2019 |
| Priority date | — |
| Expiry date | Oct 25, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a layout pattern of a static random access memory (SRAM). The layout pattern includes a first inverter and a second inverter constituting a latch circuit, wherein the latch circuit includes four transistors, a first access transistor (PG1) and a second access transistor (PG2) being electrically connected to the latch circuit, wherein the first access transistor is electrically connected to a first word line and a first bit line, and the second access transistor is electrically connected to a second word line and a second bit line, the first access transistor has a first gate length, the first access transistor has a second gate length, and the first gate length is different from the second gate length, and two read transistors series connected to each other, wherein one of the two read transistors is connected to the latch circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.