Clock and data recovery of sub-rate data
US10396803B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Oct 19, 2018 |
| Grant date | Aug 27, 2019 |
| Priority date | — |
| Expiry date | Oct 19, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock and data recovery (CDR) circuit operates to recover a clock and sample data from full-rate and sub-rate data signals. The CDR circuit selectively shifts one or more of the sampling clocks based on the rate of a received data signal, facilitating accurate sampling of sub-rate data signals. A masking circuit selectively masks data output bits clocked by a selection of the sampling clocks, thereby outputting relevant sampled data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.