Systems and methods for writing zeros to a memory array
US10402116B2 · kind B2 · utility
2Cited by
7References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2017 |
| Grant date | Sep 3, 2019 |
| Priority date | — |
| Expiry date | Dec 11, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may include a memory array that includes multiple memory cells. The memory device may also include multiple sense amplifiers that, in operation, may each be connected to one or more memory cells. The sense amplifiers may be designed to assist in writing logical zeros to the multiple memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.