Accelerating memory fault resolution by performing fast re-fetching
US10402263B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2017 |
| Grant date | Sep 3, 2019 |
| Priority date | — |
| Expiry date | Mar 1, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/702
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for handling load faults in an out-of-order processor is described. The method includes detecting, by a memory ordering buffer of the out-of-order processor, a load fault corresponding to a load instruction that was executed out-of-order by the out-of-order processor; determining, by the memory ordering buffer, whether instant reclamation is available for resolving the load fault of the load instruction; and performing, in response to determining that instant reclamation is available for resolving the load fault of the load instruction, instant reclamation to re-fetch the load instruction for execution prior to attempting to retire the load instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.