Inventor · Yoqneam Illit, IL

Igor Yanover

39Patents
5h-index
79Co-inventors
68Inventor score

Filing activity: Sep 22, 2010 → Jan 22, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US11086623B2 Systems, methods, and apparatuses for tile matrix multiplication and accumulation Physics 31 Active
US8972697B2 Gather using index array and finite state machine Physics 12 Active
US11567765B2 Systems, methods, and apparatuses for tile load Physics 6 Active
US11977886B2 Systems, methods, and apparatuses for tile store Physics 5 Active
US11714642B2 Systems, methods, and apparatuses for tile store Physics 5 Active
US11288069B2 Systems, methods, and apparatuses for tile store Physics 5 Active
US9626333B2 Scatter using index array and finite state machine Physics 4 Active
US10152451B2 Scatter using index array and finite state machine Physics 3 Active
US9753889B2 Gather using index array and finite state machine Physics 3 Active
US9996127B2 Method and apparatus for proactive throttling for improved power transitions in a processor core Emerging Cross-Sectional Technologies 2 Active
US10146737B2 Gather using index array and finite state machine Physics 2 Active
US11392380B2 Apparatuses, methods, and systems to precisely monitor memory store accesses Physics 2 Active
US10402263B2 Accelerating memory fault resolution by performing fast re-fetching Physics 1 Active
US11915000B2 Apparatuses, methods, and systems to precisely monitor memory store accesses Physics 1 Active
US10942738B2 Accelerator systems and methods for matrix operations Physics 1 Active
US9411728B2 Methods and apparatus for efficient communication between caches in hierarchical caching design Physics 1 Active
US12182571B2 Systems, methods, and apparatuses for tile load, multiplication and accumulation Physics 0 Active
US11544062B2 Apparatus and method for store pairing with reduced hardware requirements Physics 0 Active
US12271735B2 Apparatuses, methods, and systems toprecisely monitor memory store accesses Physics 0 Active
US11809549B2 Apparatus and method for power virus protection in a processor Emerging Cross-Sectional Technologies 0 Active
US10303605B2 Increasing invalid to modified protocol occurrences in a computing system Physics 0 Active
US11656998B2 Memory tagging metadata manipulation Physics 0 Active
US11681533B2 Restricted speculative execution mode to prevent observable side effects Physics 0 Active
US8516577B2 Regulating atomic memory operations to prevent denial of service attack Physics 0 Active
US10936041B2 Adjusting a throttling threshold in a processor Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.