Memory access for busy memory by receiving data from cache during said busy period and verifying said data utilizing cache hit bit or cache miss bit
US10402324B2 · kind B2 · utility
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22References
8Claims
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Key dates
| Filing date | Oct 31, 2013 |
| Grant date | Sep 3, 2019 |
| Priority date | — |
| Expiry date | Apr 9, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to an example, a processor generates a memory access request and sends the memory access request to a memory module. The processor receives data from the memory module in response to the memory access request when a memory device in the memory module for the memory access request is busy and unable to execute the memory access request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.