Memory controller with flexible address decoding
US10403333B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2016 |
| Grant date | Sep 3, 2019 |
| Priority date | — |
| Expiry date | Dec 14, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller includes a host interface for receiving memory access requests including access addresses, a memory interface for providing memory accesses to a memory system, and an address decoder coupled to the host interface for programmably mapping the access addresses to selected ones of a plurality of regions. The address decoder is programmable to map the access addresses to a first region having a non-power-of-two size using a primary decoder and a secondary decoder each having power-of-two sizes, and providing a first region mapping signal in response. A command queue stores the memory access requests and region mapping signals. An arbiter picks the memory access requests from the command queue based on a plurality of criteria, which are evaluated based in part on the region mapping signals, and provides corresponding memory accesses to the memory interface in response.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.