Methods of forming self-aligned vias and air gaps
US10403542B2 · kind B2 · utility
3Cited by
2References
19Claims
0Family size
Inventors
Key dates
| Filing date | Jun 8, 2018 |
| Grant date | Sep 3, 2019 |
| Priority date | — |
| Expiry date | Jun 8, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53266
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A first metallization layer comprises a set of first conductive lines that extend along a first direction on a first dielectric layer on a substrate. Pillars are formed on recessed first dielectric layers and a second dielectric layer covers the pillars. A dual damascene etch provides a contact hole through the second dielectric layer and an etch removes the pillars to form air gaps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.