Dual-damascene zero-misalignment-via process for semiconductor packaging

US10403564B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Aleksandar Aleksov · Chandler, US
• Hiroki Tanaka · Osaka, JP
• Robert Alan May · Chandler, US
• Kristof Darmawikarta · Chandler, US
• Changhua Liu · Chandler, US
• Chung Kwang Christopher Tan · Chandler, US
• Srinivas V. Pietambaram · Gilbert, US
• Sri Ranga Sai Boyapati · Chandler, US

Key dates

• Filing date: Dec 30, 2017
• Grant date: Sep 3, 2019
• Expiry date: Jan 26, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2224/02372
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.