Patent · US Active

Stacked package assembly with voltage reference plane

US10403604B2 · kind B2 · utility

1Cited by

1References

18Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Bok Eng Cheah · Air Itam, MY
Jackson Chung Peng Kong · Merang, MY
Ping Ping Ooi · Butterworth, MY
Kooi Chi Ooi · Air Itam, MY
Shanggar Periaman · Butterworth, MY

Key dates

Filing date	Nov 5, 2015
Grant date	Sep 3, 2019
Priority date	—
Expiry date	Nov 5, 2035

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/18162
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Embodiments of the present disclosure are directed toward a stacked package assembly for embedded dies and associated techniques and configurations. In one embodiment, stacked package assembly may comprise a first die package and a second die package stacked one upon the other with plural interconnections between them; and a voltage reference plane embedded in at least one of the first and second die packages in proximity and generally parallel to the other of the first and second die packages.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.