Ping Ping Ooi
18Patents
2h-index
24Co-inventors
50Inventor score
Filing activity: Jun 29, 2012 → Oct 27, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8890302B2 | Hybrid package transmission line circuits | Electricity | 3 | Active |
| US11121074B2 | Packaged die stacks with stacked capacitors and methods of assembling same | Electricity | 2 | Active |
| US10388636B2 | Integrating system in package (SIP) with input/output (IO) board for platform miniaturization | Electricity | 2 | Active |
| US10317938B2 | Apparatus utilizing computer on package construction | Electricity | 2 | Active |
| US10541200B2 | Over-molded IC packages with embedded voltage reference plane and heater spreader | Electricity | 1 | Active |
| US10593618B2 | Packaged die stacks with stacked capacitors and methods of assembling same | Electricity | 1 | Active |
| US10998261B2 | Over-molded IC package with in-mold capacitor | Electricity | 1 | Active |
| US11164827B2 | Substrate with gradiated dielectric for reducing impedance mismatch | Electricity | 1 | Active |
| US10403604B2 | Stacked package assembly with voltage reference plane | Electricity | 1 | Active |
| US11521932B2 | Composite bridge die-to-die interconnects for integrated-circuit packages | Electricity | 0 | Active |
| US10916524B2 | Stacked dice systems | Electricity | 0 | Active |
| US9543244B2 | Hybrid package transmission line circuits | Electricity | 0 | Active |
| US12142570B2 | Composite bridge die-to-die interconnects for integrated-circuit packages | Electricity | 0 | Active |
| US11837458B2 | Substrate with gradiated dielectric for reducing impedance mismatch | Electricity | 0 | Active |
| US12002793B2 | Integrating system in package (SiP) with input/output (IO) board for platform miniaturization | Electricity | 0 | Active |
| US10980108B2 | Multi-conductor interconnect structure for a microelectronic device | Electricity | 0 | Active |
| US11355458B2 | Interconnect core | Electricity | 0 | Active |
| US11114421B2 | Integrating system in package (SiP) with input/output (IO) board for platform miniaturization | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.