Semiconductor memory device and method of manufacturing the same
US10403634B2 · kind B2 · utility
7Cited by
17References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 25, 2018 |
| Grant date | Sep 3, 2019 |
| Priority date | — |
| Expiry date | May 25, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a cell array region and a peripheral circuit region. The cell array region includes an electrode structure including a plurality of electrodes sequentially stacked on a body conductive layer, and vertical structures penetrating the electrode structure so as to be connected to the body conductive layer. The peripheral circuit region includes a remaining substrate on the body conductive layer. The remaining substrate includes a buried insulating layer, and a peripheral active layer that is provided on the buried insulating layer and is substantially single-crystalline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.