Three-dimensional semiconductor memory devices
US10403719B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2017 |
| Grant date | Sep 3, 2019 |
| Priority date | — |
| Expiry date | Oct 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/63
Abstract
A three-dimensional semiconductor memory device includes common source regions, an electrode structure between the common source regions, first channel structures penetrating the electrode structure, and second channel structures between the first channel structures and penetrating the electrode structures. The electrode structure includes electrodes vertically stacked on a substrate. The first channel structures include a first semiconductor pattern and a first vertical insulation layer. The second channel structures include a second vertical insulation layer surrounding a second semiconductor pattern. The second vertical insulation layer has a bottom surface lower than a bottom surface of the first vertical insulation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.