Method of forming a gate structure of a semiconductor device
US10403737B2 · kind B2 · utility
1Cited by
9References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 16, 2018 |
| Grant date | Sep 3, 2019 |
| Priority date | — |
| Expiry date | Nov 16, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.