Parallel pipeline logic circuit for generating CRC values utilizing lookup table
US10404278B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2016 |
| Grant date | Sep 3, 2019 |
| Priority date | — |
| Expiry date | Feb 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6505
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
CRC generation circuitry includes a lookup-table storing N-bit CRC values for M one-hot data frames. N AND gates for each bit of a M-bit data frame receive that bit of the M-bit data frame and a different bit of a N-bit CRC value from the lookup-table corresponding to a position of the bit in the M-bit data frame. N exclusive-OR gates each receive output from one of the N AND gates for each bit of the M-bit data frame. The N exclusive-OR gates generate a final N-bit CRC value for the M-bit data frame. The CRC value is therefore generated with a purely combinational circuit, without clock cycle latency. Area consumption is small due to the small lookup-table, which itself permits use of any generator polynomial, and is independent of the width of the received data frame. This device can also generate a combined CRC for multiple frames.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.