Division synthesis
US10409556B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 30, 2017 |
| Grant date | Sep 10, 2019 |
| Priority date | — |
| Expiry date | Oct 30, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5356
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A binary logic circuit for determining the ratio x/d in accordance with a rounding scheme, where x is a variable integer input of bit length w and d is a fixed positive integer of the form 2n±1, the binary logic circuit being configured to form the ratio as a plurality of bit slices, the bit slices collectively representing the ratio, wherein the binary logic circuit is configured to generate each bit slice according to a first modulo operation for calculating mod(2n±1) of a respective bit selection of the input x and in dependence on a check for a carry bit, wherein the binary logic circuit is configured to, responsive to the check, selectively combine a carry bit with the result of the first modulo operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.