Instructions having support for floating point and integer data types in the same register
US10409614B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2017 |
| Grant date | Sep 10, 2019 |
| Priority date | — |
| Expiry date | Apr 24, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising instruction decode logic to decode a single instruction including multiple operands into a single decoded instruction, the multiple operands having differing precisions and a general-purpose graphics compute unit including a first logic unit and a second logic unit, the general-purpose graphics compute unit to execute the single decoded instruction, wherein to execute the single decoded instruction includes to perform a first instruction operation on a first set of operands of the multiple operands at a first precision and a simultaneously perform second instruction operation on a second set of operands of the multiple operands at a second precision.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.