Apparatus and method for efficiently implementing a processor pipeline

US10409763B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Patrick P. Lai · Fremont, US
• Ethan Schuchman · Santa Clara, US
• David Keppel · Seattle, US
• Denis M. Khartikov · San Jose, US
• Polychronis Xekalakis · San Jose, US
• Joshua B. Fryman · Corvallis, US
• Allan D. Knies · San Francisco, US
• Naveen Neelakantam · Mountain View, US
• Gregor Stellpflug · Braunschweig, DE
• John H. Kelm · Belmont, US
• Mirem Hyuseinova Seidahmedova · Barcelona, ES
• Demos Pavlou · Barcelona, ES
• Jaroslaw Topp

Key dates

• Filing date: Jun 30, 2014
• Grant date: Sep 10, 2019
• Expiry date: May 23, 2036

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F9/46
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Various different embodiments of the invention are described including: (1) a method and apparatus for intelligently allocating threads within a binary translation system; (2) data cache way prediction guided by binary translation code morphing software; (3) fast interpreter hardware support on the data-side; (4) out-of-order retirement; (5) decoupled load retirement in an atomic OOO processor; (6) handling transactional and atomic memory in an out-of-order binary translation based processor; and (7) speculative memory management in a binary translation based out of order processor.