David Keppel
38Patents
10h-index
54Co-inventors
78Inventor score
Filing activity: Feb 28, 1997 → Jun 30, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5905855A | Method and apparatus for correcting errors in computer systems | Physics | 101 | Expired |
| US6738892B1 | Use of enable bits to control execution of selected instructions | Physics | 92 | Expired |
| US6415379B1 | Method and apparatus for maintaining context while executing translated instructions | Physics | 51 | Expired |
| US6363336B1 | Fine grain translation discrimination | Physics | 50 | Expired |
| US6356615B1 | Programmable event counter system | Physics | 33 | Expired |
| US9342403B2 | Method and apparatus for managing a spin transfer torque memory | Physics | 31 | Active |
| US6668287B1 | Software direct memory access | Physics | 24 | Expired |
| US7640450B1 | Method and apparatus for handling nested faults | Physics | 23 | Expired |
| US6714904B1 | System for using rate of exception event generation during execution of translated instructions to control optimization of the translated instructions | Physics | 21 | Expired |
| US6513110B1 | Check instruction and method | Physics | 10 | Expired |
| US6845353B1 | Interpage prologue to protect virtual address mappings | Physics | 10 | Expired |
| US9116729B2 | Handling of binary translated self modifying code and cross modifying code | Physics | 9 | Active |
| US7761857B1 | Method for switching between interpretation and dynamic translation in a processor system based upon code sequence execution counts | Physics | 7 | Expired |
| US11055232B2 | Valid bits of a translation lookaside buffer (TLB) for checking multiple page sizes in one probe cycle and reconfigurable sub-TLBS | Physics | 6 | Active |
| US9477628B2 | Collective communications apparatus and method for parallel systems | Physics | 4 | Active |
| US10409763B2 | Apparatus and method for efficiently implementing a processor pipeline | Physics | 4 | Active |
| US6829719B2 | Method and apparatus for handling nested faults | Physics | 3 | Expired |
| US10135708B2 | Technologies for performance inspection at an endpoint node | Electricity | 2 | Active |
| US7617088B1 | Interpage prologue to protect virtual address mappings | Physics | 1 | Active |
| US10135711B2 | Technologies for sideband performance tracing of network traffic | Electricity | 1 | Active |
| US9766685B2 | Controlling power consumption of a processor using interrupt-mediated on-off keying | Emerging Cross-Sectional Technologies | 1 | Active |
| US9442849B2 | Apparatus and method for reduced core entry into a power state having a powered down core cache | Emerging Cross-Sectional Technologies | 1 | Active |
| US9971599B2 | Instruction and logic for support of code modification | Physics | 1 | Active |
| US10061376B2 | Opportunistic power management for managing intermittent power available to data processing device having semi-non-volatile memory or non-volatile memory | Emerging Cross-Sectional Technologies | 1 | Active |
| US11989135B2 | Programmable address range engine for larger region sizes | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.