Skew reduction of a wave pipeline in a memory device
US10410698B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2017 |
| Grant date | Sep 10, 2019 |
| Priority date | — |
| Expiry date | Dec 7, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A wave pipeline includes a plurality of data paths, a clock signal path, and a return clock signal path. Each data path includes an input node, an output node, and a data stage between the input node and the output node. Each data path has a different delay between the input node and the output node. A first data path of the plurality of data paths has a first delay and each of the other data paths of the plurality of data paths have a delay less than the first delay. The clock signal path provides a clock signal to the data stage of each data path. The return clock signal path provides a return clock signal from the data stage of the first data path. The return clock signal triggers data out of the data stage of each data path of the plurality of data paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.