Inter-chip alignment

US10410989B2 · kind B2 · utility

Assignees

• University of Notre Dame du Lac · US
• Indiana Integrated Circuits, LLC · US

Inventors

• Douglas C. Hall · South Bend, US
• Gary H. Bernstein · Granger, US
• Anthony Hoffman · South Bend, US
• Scott Howard · South Bend, US
• Jason M. Kulick · South Bend, US

Key dates

• Filing date: Apr 21, 2017
• Grant date: Sep 10, 2019
• Expiry date: Apr 21, 2037

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02P70/50
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

First, second, and third integrated devices each include one or more interconnecting structure. Each interconnecting structure includes (i) one or more interconnecting nodules extending from an edge surface of the device, (ii) one or more interconnect voids formed in an edge surface of the device, or (iii) both (i) and (ii). The one or more interconnecting structures on each of the first and second device is mated with the one or more interconnecting structures on the second device. The first integrated device includes a signal output, the third integrated device includes a signal input; and the second integrated device includes a conductor for conducting a signal from the signal output to the signal input.