Semiconductor memory device including a selection element pattern confined to a hole
US10411070B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 26, 2018 |
| Grant date | Sep 10, 2019 |
| Priority date | — |
| Expiry date | Jun 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic device having a semiconductor memory device is provided. The semiconductor memory device may include a lower interlayer insulating layer having a hole; an upper interlayer insulating layer disposed on the lower interlayer insulating layer; and a memory cell stack including a lower element and an upper element, the lower element being confined to the hole of the lower interlayer insulating layer, the upper element being surrounded by the upper interlayer insulating layer. The lower element may include a lower electrode and a selection element pattern disposed on the lower electrode. The upper element may include a memory pattern disposed on the selection element pattern and an upper electrode disposed on the memory pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.