Systems and methods for improving signal margin for input buffer circuits
US10411707B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 31, 2018 |
| Grant date | Sep 10, 2019 |
| Priority date | — |
| Expiry date | Jul 31, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/45475
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input buffer circuit may include a first switch that may couple a first voltage source to an output line based on an enable signal, such that the enable signal is configured to cause the input buffer circuit to operate. The input buffer circuit may also include a first set of switches that may couple the first voltage source to the output line based on the enable signal and an input signal, wherein the first switch and the first set of switches may couple the first voltage source to the output line in response to the input signal being greater than an input reference signal. The input buffer circuit may also include a switch that may couple a second voltage source to the output line in response to the input signal being less than the input reference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.