FPGA having a virtual array of logic tiles, and method of configuring and operating same
US10411711B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2018 |
| Grant date | Sep 10, 2019 |
| Priority date | — |
| Expiry date | May 9, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17736
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprising a physical array of logic tiles, wherein each logic tile includes a perimeter and a plurality of external I/O disposed in a layout on the perimeter of the logic tile wherein the layout of the external I/O of each logic tile is identical. The physical array includes a first virtual array of logic tiles, programmed to perform data processing operations, including a first plurality of logic tiles of the physical array. The physical array also includes a second virtual array of logic tiles, programmed to perform second operations, including a second plurality of logic tiles of the physical array. The logic tiles of the second plurality are different from the logic tiles of the first plurality. In one embodiment, performance of the data processing operations of the first virtual array is independent from performance of the second operations of the second virtual array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.