Ethernet physical layer device having integrated physical coding and forward error correction sub-layers
US10411832B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2016 |
| Grant date | Sep 10, 2019 |
| Priority date | — |
| Expiry date | Oct 7, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0043
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Disclosed are Ethernet physical layer devices (e.g., a transceiver, a receiver and a transmitter) with integrated physical coding and forward error correction sub-layers. Each physical layer device includes a physical coding sub-layer (PCS), a forward error correction sub-layer (FEC) and integration block(s). Each integration block halts, for some number of clock cycles, a data stream in portions of a data path (e.g., portions of a transmitter (TX) data path or portions a receiver (RX) data path) within the PCS and the FEC in order to compensate for processing of that data stream by a data processor (e.g., a code word mark (CWM) inserter or a CWM remover) contained in the portion of the data path within the FEC. Use of such integration block(s) eliminates the need for redundant components in the PCS and FEC, thereby reducing latency, costs and chip area consumption. Also disclosed are associated methods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.