Method and apparatus for hardware management of multiple memory pools
US10417141B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2017 |
| Grant date | Sep 17, 2019 |
| Priority date | — |
| Expiry date | May 22, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/68
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system for managing at least first and second memories includes a caching manager and a translation lookaside buffer (TLB). The caching manager comprises hardware configured to transfer data between the memories and is configured to monitor accesses to the first memory by a processing device and transfer data in a frequently accessed region at a first address in the first memory to a region at a second address in the second memory. When the data has not been transferred to the second memory, the TLB stores a virtual address and a corresponding address in the first memory. However, when the data has been transferred to the second memory, the TLB stores the virtual address and a corresponding address in the second memory. A mapping between the addresses in the first and second memories may be stored in a shadow-address table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.