Patent · US Active

Power and scan resource reduction in integrated circuit designs having shift registers

US10417363B1 · kind B1 · utility

3Cited by

26References

14Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Jagjot Kaur · Milpitas, US
Priyanka Dasgupta · Bengaluru, IN
Pratyush Aditya Kothamasu · Milpitas, US
Vivek Chickermane · Ithaca, US

Key dates

Filing date	Dec 27, 2016
Grant date	Sep 17, 2019
Priority date	—
Expiry date	Mar 23, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/27
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments relate to methodologies for applying multibit cell merging to functional shift registers, thereby saving area, reducing scan-wirelength, saving power and reducing wiring congestion in integrated circuit designs. In embodiments, during synthesis, shift registers in a design are identified. In these and other embodiments, in identified shift registers, functional shift register flip-flops are merged into non-scan multi-bit flip-flops using a physically aware approach.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.