Inventor · Ithaca, NY, US

Vivek Chickermane

53Patents
10h-index
48Co-inventors
74Inventor score

Filing activity: Sep 11, 2006 → Feb 24, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US7739629B2 Method and mechanism for implementing electronic designs having power information specifications background Physics 28 Active
US8904256B1 Method and apparatus for low-pin count testing of integrated circuits Physics 24 Active
US8650524B1 Method and apparatus for low-pin count testing of integrated circuits Physics 22 Active
US7926012B1 Design-For-testability planner Physics 19 Active
US8468404B1 Method and system for reducing switching activity during scan-load operations Physics 18 Active
US7779381B2 Test generation for low power circuits Physics 15 Active
US7979764B2 Distributed test compression for integrated circuits Physics 14 Active
US7877715B1 Method and apparatus to use physical design information to detect IR drop prone test patterns Physics 14 Active
US7693676B1 Low power scan test for integrated circuits Physics 13 Active
US8732632B1 Method and apparatus for automated extraction of a design for test boundary model from embedded IP cores for hierarchical and three-dimensional interconnect test Physics 11 Active
US8516422B1 Method and mechanism for implementing electronic designs having power information specifications background Physics 8 Active
US8001433B1 Scan testing architectures for power-shutoff aware systems Physics 7 Active
US8271226B2 Testing state retention logic in low power systems Physics 7 Active
US9702934B1 Reducing mask data volume with elastic compression Physics 6 Active
US7886263B1 Testing to prescribe state capture by, and state retrieval from scan registers Physics 5 Active
US9606179B1 Method and system for improving efficiency of XOR-based test compression using an embedded serializer-deserializer Physics 5 Active
US7944285B1 Method and apparatus to detect manufacturing faults in power switches Physics 5 Active
US9470756B1 Method for using sequential decompression logic for VLSI test in a physically efficient construction Physics 5 Active
US8615692B1 Method and system for analyzing test vectors to determine toggle counts Physics 5 Active
US8296703B1 Fault modeling for state retention logic Physics 5 Active
US8286123B1 Method and apparatus to use physical design information to detect IR drop prone test patterns Physics 4 Active
US8296694B1 System and method for automated synthesis of circuit wrappers Physics 4 Active
US9501590B1 Systems and methods for testing integrated circuit designs Physics 4 Active
US10417363B1 Power and scan resource reduction in integrated circuit designs having shift registers Physics 3 Active
US9470754B1 Elastic compression-optimizing tester bandwidth with compressed test stimuli using overscan and variable serialization Physics 3 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.