Semiconductor device having interconnection in package and method for manufacturing the same
US10418087B2 · kind B2 · utility
0Cited by
20References
23Claims
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Key dates
| Filing date | Jul 3, 2017 |
| Grant date | Sep 17, 2019 |
| Priority date | — |
| Expiry date | Nov 9, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.