Asymmetric pass field-effect transistor for nonvolatile memory
US10418110B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jul 3, 2018 |
| Grant date | Sep 17, 2019 |
| Priority date | — |
| Expiry date | Jul 3, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0433
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of performing an operation on a non-volatile memory (NVM) cell of a memory device is disclosed. The pass transistor of the NVM cell is an asymmetric transistor including a source with a halo implant. The source of the pass transistor is coupled to a common source line (CSL) that is shared among NVM cells of a sector of NVM cells. The operation may be performed by applying a first signal to a word line (WLS) coupled to a gate of a memory transistor of the NVM cell and applying a second signal to a bit line (BL) coupled to a drain of the memory transistor of the NVM cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.