Non-volatile memory structure in silicon-on-insulator (SOI) technology
US10418465B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2018 |
| Grant date | Sep 17, 2019 |
| Priority date | — |
| Expiry date | May 3, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Certain aspects of the present disclosure provide a memory device. One example memory device generally includes a first semiconductor region having a first region, a second region, and a third region, the second region being between the first region and the third region and having a different doping type than the first region and the third region. In certain aspects, the memory device also includes a first non-insulative region, a first insulative region being disposed between the first non-insulative region and the first semiconductor region. In certain aspects, the memory device may include a second non-insulative region, and a second insulative region disposed between the second region and the second non-insulative region, wherein the first insulative region and the second insulative region are disposed adjacent to opposite sides of the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.