System and method for calibrating pulse width and delay
US10418981B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2017 |
| Grant date | Sep 17, 2019 |
| Priority date | — |
| Expiry date | Nov 23, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00019
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method for calibrating a duration of a pulse or a delay. A reference clock signal includes a sequence of reference pulses, and controls a switch in a first charge pump that is configured to charge a first capacitor. Each of a sequence of test pulses controls a switch in a second charge pump that is configured to charge a second capacitor. At the end of each charging cycle, the respective capacitor voltages are compared and the duration of the test pulses is adjusted, by a feedback circuit, in a direction tending to make the capacitor voltages equal. When the capacitor voltages are equal, the ratio of the lengths of the reference pulses and test pulses equals the ratio of the capacitances, if the charge pumps deliver the same current when switched on.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.