Chih-Wei Yao
31Patents
7h-index
17Co-inventors
62Inventor score
Filing activity: Dec 17, 2007 → Jan 2, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8564471B1 | High resolution sampling-based time to digital converter | Electricity | 30 | Active |
| US9240914B2 | Communication system with frequency synthesis mechanism and method of operation thereof | Electricity | 17 | Active |
| US7847650B2 | Low phase-noise oscillator | Electricity | 14 | Active |
| US10965297B1 | Sigma-delta modulation quantization error reduction technique for fractional-N phase-locked loop (PLL) | Electricity | 10 | Active |
| US10623010B2 | System and method of calibrating input signal to successive approximation register (SAR) analog-to-digital converter (ADC) in ADC-assisted time-to- digital converter (TDC) | Electricity | 9 | Active |
| US10581418B2 | System and method for fast converging reference clock duty cycle correction for digital to time converter (DTC)-based analog fractional-N phase-locked loop (PLL) | Electricity | 9 | Active |
| US8970421B1 | High resolution sampling-based time to digital converter | Electricity | 7 | Active |
| US9746832B1 | System and method for time-to-digital converter fine-conversion using analog-to-digital converter (ADC) | Electricity | 7 | Active |
| US10996634B2 | System and method for fast-converging digital-to-time converter (DTC) gain calibration for DTC-based analog fractional-N phase lock loop (PLL) | Electricity | 7 | Active |
| US10917078B2 | System and method for fast converging reference clock duty cycle correction for digital to time converter (DTC)-based analog fractional-N phase-locked loop (PLL) | Electricity | 6 | Active |
| US10418981B2 | System and method for calibrating pulse width and delay | Electricity | 5 | Active |
| US8564342B2 | Reference clock compensation for fractional-N phase lock loops (PLLs) | Electricity | 5 | Active |
| US10841072B2 | System and method for providing fast-settling quadrature detection and correction | Electricity | 4 | Active |
| US8461886B1 | Circuit and circuit method for reduction of PFD noise contribution for ADPLL | Electricity | 4 | Active |
| US9219484B2 | Reference clock compensation for fractional-N phase lock loops (PLLS) | Electricity | 3 | Active |
| US10009036B2 | System and method of calibrating input signal to successive approximation register (SAR) analog-to-digital converter (ADC) in ADC-assisted time-to-digital converter (TDC) | Electricity | 2 | Active |
| US11063599B2 | Apparatus and method for automatic search of sub-sampling phase locked loop (SS-PLL) locking acquisition | Electricity | 2 | Active |
| US11115005B2 | Ring voltage controlled oscillator (VCO) startup helper circuit | Electricity | 1 | Active |
| US11431344B2 | Apparatus and method for automatic search of sub-sampling phase locked loop (SS-PLL) locking acquisition | Electricity | 1 | Active |
| US11233627B2 | System and method for providing fast-settling quadrature detection and correction | Electricity | 1 | Active |
| US9356555B2 | Fine tuning control for a digitally controlled oscillator | Electricity | 1 | Active |
| US9379662B2 | System and method using temperature tracking for a controlled oscillator | Electricity | 0 | Active |
| US11050428B2 | Synchronous sampling in-phase and quadrature-phase (I/Q) detection circuit | Electricity | 0 | Active |
| US10725432B2 | System and method for fast-converging digital-to-time converter (DTC) gain calibration for DTC-based analog fractional-N phase lock loop (PLL) | General | 0 | Revoked |
| US11354476B2 | Simulation method of an electron device | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.