Timing error measurement in current steering digital to analog converters
US10419011B1 · kind B1 · utility
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4References
20Claims
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Key dates
| Filing date | Aug 21, 2018 |
| Grant date | Sep 17, 2019 |
| Priority date | — |
| Expiry date | Aug 21, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/747
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An example timing error measurement system includes a digital-to-analog converter (DAC) having a plurality of current steering circuits, the DAC responsive to a clock signal, a one-bit comparator coupled to a differential output of the DAC, a filter coupled to an output of the one-bit comparator, control logic coupled to an output of the filter, and a delay line coupled to an output of the control logic. An output of the delay line is coupled to an input of the one-bit comparator. The delay line is configured to delay the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.