Memory device with a multi-mode communication mechanism
US10419574B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2017 |
| Grant date | Sep 17, 2019 |
| Priority date | — |
| Expiry date | Dec 22, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W88/16
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory array including a first communication circuit element configured to communicate a first signal between components in the memory device; a second communication circuit element configured to communicate a second signal between the components in the memory device; and a configurable grouping mechanism coupled to the first communication circuit element and the second communication circuit element, the configurable grouping mechanism configured to select between: operating the first communication circuit element and the second communication circuit element independent of each other, where in the first signal and the second signal are independent signals, and operating the first communication circuit element and the second communication circuit element as a group, wherein the first signal corresponds to the second signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.