LDO regulator using NMOS transistor
US10423178B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 6, 2018 |
| Grant date | Sep 24, 2019 |
| Priority date | — |
| Expiry date | Nov 6, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/461
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A low dropout (LDO) regulator includes an NMOS transistor, a resistor ladder, an error amplifier and a gate boosting circuit. The NMOS transistor is configured for receiving an input voltage to generate an output voltage. The resistor ladder, coupled to the NMOS transistor, is configured for generating a feedback signal according to a level of the output voltage. The error amplifier, coupled to the resistor ladder, is configured for receiving the feedback signal from the resistor ladder to generate a control signal. The gate boosting circuit, coupled between the NMOS transistor and the error amplifier, is configured for boosting the control signal to control the NMOS transistor, so as to pull the output voltage to a target level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.