Fault tolerant processor for real-time systems
US10423417B2 · kind B2 · utility
2Cited by
5References
11Claims
0Family size
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Key dates
| Filing date | Jun 17, 2015 |
| Grant date | Sep 24, 2019 |
| Priority date | — |
| Expiry date | Jun 29, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/183
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fault tolerant multi-threaded processor uses the temporal and/or spatial separation of instructions running in two or more different threads. An instruction is fetched, decoded and executed by each of two or more threads to generate a result for each of the two or more threads. These results are then compared using comparison hardware logic and if there is a mismatch between the results obtained, then an error or event is raised. The comparison is performed on an instruction by instruction basis so that errors are identified (and hence can be resolved) quickly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.