Semiconductor memory device and control method of semiconductor memory device
US10424384B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2018 |
| Grant date | Sep 24, 2019 |
| Priority date | — |
| Expiry date | Aug 27, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes an n-type semiconductor region, first to fourth conductive layers above the n-type semiconductor region, a p-type semiconductor region, a semiconductor layer between the n-type semiconductor region and the p-type semiconductor region and extending through the conductive layers, charge storage regions between the conductive layers and the semiconductor layer, a control circuit that executes a first read sequence and a second read sequence following the first read sequence, a comparison circuit that compares the first data read in the first read sequence to the second data read in the second read sequence, and a determination circuit that selects one of the first data and the second data as a true read value. The first and second read sequences each have an off step and an off voltage applied during the first read sequence is different from an off voltage applied during the second read sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.