Method of integrating a charge-trapping gate stack into a CMOS flow

US10424592B2 · kind B2 · utility

Assignee

• LONGITUDE FLASH MEMORY SOLUTIONS LTD. · IE

Inventor

• Krishnaswamy Ramkumar · San Jose, US

Key dates

• Filing date: Jul 24, 2018
• Grant date: Sep 24, 2019
• Expiry date: Jul 24, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack, wherein the cap layer comprises a multi-layer cap layer including at least a first cap layer overlying the charge-trapping layer, and a second cap layer overlying the first cap layer; patterning the cap layer and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to oxidize the first cap layer to form a blocking oxide overlying the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.