Die-to-die interface configuration and methods of use thereof
US10424921B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2017 |
| Grant date | Sep 24, 2019 |
| Priority date | — |
| Expiry date | Dec 2, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/08135
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor die including: a die-to-die interface including an input/output (I/O) circuitry area and an electrical contact area; wherein the electrical contact area includes an array of electrical contacts disposed on a side of the semiconductor die; and wherein the I/O circuitry area includes a plurality of drivers, each of the drivers coupled to at least one electrical contact in the electrical contact area, and a plurality of electrostatic discharge (ESD) protection devices, each of the ESD protection devices coupled to a respective driver, further wherein the I/O circuitry area and the electrical contact area are separated in a top-down view of the semiconductor die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.