Scan flip-flop and scan test circuit including the same
US10429443B2 · kind B2 · utility
1Cited by
17References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2017 |
| Grant date | Oct 1, 2019 |
| Priority date | — |
| Expiry date | Dec 9, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35625
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop is configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.