Dal-Hee Lee
20Patents
4h-index
26Co-inventors
59Inventor score
Filing activity: Mar 5, 2013 → Jul 11, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9460259B2 | Methods of generating integrated circuit layout using standard cell library | Electricity | 17 | Active |
| US8952423B2 | Semiconductor device having decoupling capacitors and dummy transistors | Electricity | 6 | Active |
| US10651201B2 | Integrated circuit including interconnection and method of fabricating the same, the interconnection including a pattern shaped and/or a via disposed for mitigating electromigration | Electricity | 4 | Active |
| US9753086B2 | Scan flip-flop and scan test circuit including the same | Electricity | 4 | Active |
| US10553574B2 | Standard cell for removing routing interference between adjacent pins and device including the same | Electricity | 4 | Active |
| US11335673B2 | Integrated circuits having cross-couple constructs and semiconductor devices including integrated circuits | Electricity | 3 | Active |
| US9831877B2 | Integrated circuit and semiconductor device including the same | Electricity | 2 | Active |
| US11101267B2 | Integrated circuit including multiple-height cell and method of manufacturing the integrated circuit | Electricity | 1 | Active |
| US11387817B2 | Latch circuit, flip-flop circuit including the same | Electricity | 1 | Active |
| US9379705B2 | Integrated circuit and semiconductor device including the same | Electricity | 1 | Active |
| US10429443B2 | Scan flip-flop and scan test circuit including the same | Electricity | 1 | Active |
| US9960768B2 | Integrated circuit and semiconductor device including the same | Electricity | 1 | Active |
| US11996846B2 | Latch circuit, flip-flop circuit including the same | Electricity | 0 | Active |
| US9665678B2 | Method and program for designing integrated circuit | Physics | 0 | Active |
| US11287474B2 | Scan flip-flop and scan test circuit including the same | Electricity | 0 | Active |
| US11955471B2 | Integrated circuits having cross-couple constructs and semiconductor devices including integrated circuits | Electricity | 0 | Active |
| US11189639B2 | Integrated circuit including interconnection and method of fabricating the same, the interconnection including a pattern shaped for mitigating electromigration | Electricity | 0 | Active |
| US10108772B2 | Methods of generating integrated circuit layout using standard cell library | Electricity | 0 | Active |
| US11031385B2 | Standard cell for removing routing interference between adjacent pins and device including the same | Electricity | 0 | Active |
| US10192860B2 | Engineering change order (ECO) cell, layout thereof and integrated circuit including the ECO cell | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.