Optical mask validation
US10429743B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2017 |
| Grant date | Oct 1, 2019 |
| Priority date | — |
| Expiry date | Nov 30, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An embodiment of the invention may include a method for ensuring semiconductor design integrity. The method may include analyzing a photomask design for a semiconductor circuit. The photomask may include an electrical design necessary for the operation of the semiconductor circuit, and white space, which has no electrical design. The method may include inserting an optical design into the white space of the photomask design for the semiconductor circuit. The optical design may have known optical patterns for validating the semiconductor circuit design. In an embodiment of the invention, the optical design may be physically isolated from the electrical design. In another embodiment of the invention, the optical design may comprise one or more photomask layers and overlay the electrical design. In another embodiment of the invention, the optical design may comprise covershapes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.