Computing system and processor with fast power surge detection and instruction throttle down to provide for low cost power supply unit
US10429912B2 · kind B2 · utility
0Cited by
8References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2017 |
| Grant date | Oct 1, 2019 |
| Priority date | — |
| Expiry date | Dec 18, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor is described that includes a quick signal path from an input of the processor to logic circuitry within the processor. The input is to receive a fast throttle down signal. The logic circuitry is to throttle down a rate at which the processor issues instructions for execution in response to the fast throttle down signal. The quick signal path is to impose practicably minimal propagation delay of the fast throttle down signal within the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.