Processor system and fault detection method thereof
US10430301B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2017 |
| Grant date | Oct 1, 2019 |
| Priority date | — |
| Expiry date | Sep 1, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a processor system including a first processor driven by a first driving voltage and a first driving clock, a second processor driven by a second driving voltage and a second driving clock and configured to perform an identical task to the first processor, and a defect detector configured to perform level synchronization or clock domain synchronization on a first output signal provided from the first processor and a second output signal provided from the second processor to compare the first and second output signals, wherein the first and second driving voltages are respectively provided from mutually independent power supply sources and the first and second driving clocks are respectively provided from mutually independent clock generators.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.