Young-Su KWON
44Patents
3h-index
37Co-inventors
59Inventor score
Filing activity: Dec 4, 2007 → Jul 18, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10489520B2 | Method and apparatus for injecting fault and analyzing fault tolerance | Physics | 3 | Active |
| US9575692B2 | Cache control device having fault-tolerant function and method of operating the same | Physics | 3 | Active |
| US9830218B2 | Cache memory with fault tolerance | Physics | 3 | Active |
| US7900018B2 | Embedded system and page relocation method therefor | Emerging Cross-Sectional Technologies | 2 | Active |
| US11146253B1 | Receiving circuit to process low-voltage signal with hysteresis | Electricity | 2 | Active |
| US9529654B2 | Recoverable and fault-tolerant CPU core and control method thereof | Physics | 2 | Active |
| US7958321B2 | Apparatus and method for reducing memory access conflict | Physics | 2 | Active |
| US10740167B2 | Multi-core processor and cache management method thereof | Physics | 1 | Active |
| US11341066B2 | Cache for artificial intelligence processor | Physics | 1 | Active |
| US11507429B2 | Neural network accelerator including bidirectional processing element array | Physics | 1 | Active |
| US10642782B2 | Multi-core processor and operation method thereof | Physics | 1 | Active |
| US10983878B2 | Processor for detecting and preventing recognition error | Physics | 1 | Active |
| US9632894B2 | Apparatus for error simulation and method thereof | Physics | 1 | Active |
| US9501311B2 | Apparatus and method for multicore emulation based on dynamic context switching | Physics | 1 | Active |
| US9824017B2 | Cache control apparatus and method | Physics | 1 | Active |
| US8566566B2 | Vector processing of different instructions selected by each unit from multiple instruction group based on instruction predicate and previous result comparison | Physics | 0 | Active |
| US9575852B2 | Failure recovery apparatus of digital logic circuit and method thereof | Physics | 0 | Active |
| US9823963B2 | Apparatus and method for controlling level 0 cache | Physics | 0 | Active |
| US11176395B2 | Image recognition processor including functional safety processor core and operation method thereof | Physics | 0 | Active |
| US10127098B2 | Apparatus and method for recovering functionality of central processing unit core | Physics | 0 | Active |
| US9859889B2 | Ultra low voltage digital circuit and operation method thereof | Electricity | 0 | Active |
| US9274794B2 | Processor and instruction processing method in processor | Physics | 0 | Active |
| US10430301B2 | Processor system and fault detection method thereof | Physics | 0 | Active |
| US8478970B2 | Accessing value for local variable from function call stack upon offset matching with instruction extracted stack pointer offset or from cache | Physics | 0 | Active |
| US8464006B2 | Method and apparatus for data transmission between processors using memory remapping | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.