Data retention with data migration
US10430302B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2017 |
| Grant date | Oct 1, 2019 |
| Priority date | — |
| Expiry date | Dec 6, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit is disclosed for data retention with data migration. In an example aspect, the integrated circuit includes a logic block, a memory block, and retention control circuitry coupled to the logic and memory blocks. The logic block includes multiple retention-relevant storage devices to store first data and second data. The multiple retention-relevant storage devices include a first group of retention-relevant storage devices to store the first data and a second group of retention-relevant storage devices to store the second data. The memory block maintains memory data in the memory block during a retention operational mode. The retention control circuitry causes the retention-relevant storage devices of the second group to be activated into multiple scan chains and also migrates the second data between the second group and the memory block using the multiple scan chains to accommodate transitions between the retention operational mode and a regular operational mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.