Memory device performing near-data processing using a plurality of data processing engines that independently perform data processing operations, and system including the same
US10430353B2 · kind B2 · utility
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Key dates
| Filing date | Jul 20, 2017 |
| Grant date | Oct 1, 2019 |
| Priority date | — |
| Expiry date | Nov 1, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/65
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell region including a plurality of memory cells; a memory cell controller configured to control read and write operation for the memory cell region; one or more NDP engines configured to perform a near data processing (NDP) operation for the memory cell region; a command buffer configured to store an NDP command transmitted from a host; and an engine scheduler configured to schedule the NDP operation for the one or more NDP engines according to the NDP command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.