Method and apparatus for enhancing performance by moving or adding a pipelined register stage in a cascaded chain
US10430539B1 · kind B1 · utility
2Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2016 |
| Grant date | Oct 1, 2019 |
| Priority date | — |
| Expiry date | Jun 26, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus relating generally to synthesis are described. In such a method, a directed graph for a circuit design is generated. A cascaded chain is identified in the directed graph with a timing violation. A pipeline register stage of the cascaded chain is moved (or added) to remove the timing violation. The circuit design is transformed to provide a netlist including the pipeline register stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.